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NM24C32 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
PRELIMINARY
March 1999
NM24C32 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
General Description:
The NM24C32 devices are 32,768 bits of CMOS nonvolatile electrically erasable memory. These devices offer the designer different low voltage and low power options, and they conform to all specifications in the Extended IIC 2-wire protocol. Furthermore, they are designed to minimize device pin count and simplify PC board layout requirements. The upper half of the memory can be disabled (Write Protection) by connecting the WP pin to VCC. This section of memory then becomes ROM. This communication protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s). Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability, and low power consumption.
Features:
s Extended operating voltage 2.7V - 5.5V s 400 KHz clock frequency (F) at 2.7V - 5.5V s 200A active current typical 10A standby current typical 1A standby typical (L) 0.1A standby typical (LZ) s IIC compatible interface - Provides bidirectional data transfer protocol s 32 byte page write mode - Minimizes total write time per byte s Self timed write cycle Typical write cycle time of 6ms s Hardware write protect for upper block s Endurance: 1,000,000 data changes s Data retention greater than 40 years s Packages available: 8-pin SO, 8-pin DIP s Low VCC programming lockout (3.8V - on Standard VCC devices only).
Block Diagram
VCC WP SDA START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER & COMPARATOR LOAD A2 A1 A0 WORD ADDRESS COUNTER INC E2PROM ARRAY WRITE LOCKOUT START CYCLE H.V. GENERATION TIMING &CONTROL
SCL
XDEC
R/W
YDEC
CK DIN DATA REGISTER DOUT
DS500073-1
(c) 1999 Fairchild Semiconductor Corporation NM24C32 Rev. C.2
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NM24C32 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
Connection Diagram
Dual-In-Line Package (N) and 8-Pin SO Package (M8) A0 A1 A2 VSS 1 2 NM24C32 3 4 6 5 SCL SDA
DS500073-2
Pin Names
A0, A1, A2 VSS SDA Device Address Input Ground Data I/O Clock Input Write Protect Power Supply
8 7
VCC WP
SCL WP VCC
Top View See Package Number N08E and M08A
Ordering Information NM 24 C XX F LZ E XX
Package Temp. Range
Letter
N M8 None V E Blank L LZ Blank F 32 C Interface 24 NM
Description
8-Pin DIP 8-Pin SOIC 0 to 70C -40 to +125C -40 to +85C 4.5V to 5.5V 2.7V to 4.5V 2.7V to 4.5V and <1A Standby Current 100KHz 400KHz 32K with Write Protect CMOS IIC Fairchild Non-Volatile Memory
Voltage Operating Range
SCL Clock Frequency Density
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NM24C32 Rev. C.2
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NM24C32 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
Product Specifications Absolute Maximum Ratings
Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 seconds) ESD Rating -65C to +150C 6.5V to -0.3V +300C 2000V min.
Operating Conditions
Ambient Operating Temperature NM24C32 NM24C32E NM24C32V Positive Power Supply NM24C32 NM24C32L NM24C32LZ 0C to +70C -40C to +85C -40C to +125C 4.5V to 5.5V 2.7V to 4.5V 2.7V to 4.5V
Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol
ICCA ISB ILI ILO VIL VIH VOL
Parameter
Active Power Supply Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage
Test Conditions Min
fSCL = 100 kHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC -0.3 VCC x 0.7 IOL = 3 mA
Limits Typ (Note 1)
0.2 10 0.1 0.1
Units Max
1.0 50 1 1 VCC x 0.3 VCC + 0.5 0.4 mA A A A V V V
Low VCC (2.7V to 4.5V) DC Electrical Characteristics
Symbol
ICCA ISB (Note 1) ILI ILO VIL VIH VOL
Parameter
Active Power Supply Current Standby Current for L Standby Current for LZ Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage
Test Conditions Min
fSCL = 100 kHz VIN = GND or VCC VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC -0.3 VCC x 0.7 IOL = 3 mA
Limits Typ (Note 1)
0.2 1 0.1 0.1 0.1
Units Max
1.0 10 1 1 1 VCC x 0.3 VCC + 0.5 0.4 mA A A A A V V V
Capacitance TA = +25C, f = 100/400 KHz, VCC = 5V (Note 2)
Symbol
CI/O CIN
Test
Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL)
Conditions
VI/O = 0V VIN = 0V
Max
8 6
Units
pF pF
Note 1: Typical values are for TA = 25C and nominal supply voltage (5V). Note 2: This parameter is periodically sampled and not 100% tested.
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NM24C32 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
AC Conditions of Test
Input Pulse Levels Input Rise and Fall Times Input & Output Timing Levels Output Load VCC x 0.1 to VCC x 0.9 10 ns VCC x 0.5 1 TTL Gate and CL = 100 pF
Read and Write Cycle Limits (Standard and Low VCC Range - 2.7V-5.5V)
Symbol
fSCL TI
Parameter
SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs (Minimum VIN Pulse width) SCL Low to SDA Data Out Valid Time the Bus Must Be Free before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data in Hold Time Data in Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Write Cycle Time - NM24C32 - NM24C32L, NM24C32LZ
100 KHz Min Max
100 100 0.3 4.7 4.0 4.7 4.0 4.7 0 250 1 300 4.7 300 10 15 3.5
400 KHz Min Max
400 50 0.1 1.3 0.6 1.5 0.6 0.6 0 100 0.3 300 0.6 50 10 15 0.9
Units
kHz ns s s s s s s ns ns s ns s ns ms
tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tWR (Note 3)
Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the NM24C32 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address
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NM24C32 Rev. C.2
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NM24C32 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
Bus Timing
tF tHIGH tLOW SCL tLOW tR
SDA
SDA
OUT
BACKGROUND INFORMATION (IIC Bus)
As mentioned, the IIC bus allows synchronous bidirectional communication between Transmitter/Receiver using the SCL (clock) and SDA (Data I/O) lines. All communication must be started with a valid START condition, concluded with a STOP condition and acknowledged by the Receiver with an ACKNOWLEDGE condition. In addition, since the IIC bus is designed to support other devices such as RAM, EPROM, etc., the device type identifier string, or slave address, must follow the START condition. For EEPROMs, the first 4-bits of the slave address is '1010'. This is then followed by the device selection bits A2, A1 and A0.The final bit in the slave address determines the type of operation performed (READ/ WRITE). A "1" signifies a READ while a "0" signifies a WRITE. The slave address is then followed by two bytes that define the word address, which is then followed by the data byte. The EEPROMs on the IIC bus may be configured in any manner required, providing the total memory addressed does not exceed 4M bits in the Extended IIC protocol. EEPROM memory addressing is controlled by hardware configuring the A2, A1, and A0 pins (Device Address pins) with pull-up or pull-down resistors. ALL UNUSED PINS MUST BE GROUNDED (tied to VSS). Addressing an EEPROM memory location involves sending a command string with the following information: [DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK ADDRESS]-[BYTE ADDRESS] Word Page

tSU:STA tHD:STA IN
tHD:DAT
tSU:DAT
tSU:STO
tBUF tDH
tAA
DS500073-3
Definitions
8 bits (byte) of data 32 sequential addresses (one byte each) that may be programmed during a "Page Write" programming cycle. Any IIC device CONTROLLING the transfer of data (such as a microcontroller). Device being controlled (EEPROMS are always considered Slaves). Device currently SENDING data on the bus (may be either a Master or Slave). Device currently receiving data on the bus (Master or Slave).
Master
Slave Transmitter Receiver
Pin Description
SERIAL CLOCK (SCL)
The SCL input is used to clock all data into and out of the device.
SERIAL DATA (SDA)
SDA is a biderectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
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NM24C32 Rev. C.2
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NM24C32 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
Device Address Inputs (A0, A1, A2)
Device address pins A0, A1, and A2 are connected to VCC or VSS to configure the EEPROM address for multiple device configuration. A total of eight different devices can be attached to the same SDA bus.
START CONDITION
All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The NM24C32xxx continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Write Protection (WP)
If WP is tied to VCC, program WRITE operations onto the upper half of the memory will not be executed. READ operations are always available. If WP is tied to VSS, normal memory operation is enabled, READ/ WRITE over the entire memory array. This feature allows the user to assign the upper half of the memory as ROM which can be protected against accidental programming writes. When WRITE is disabled, slave address and word address will be acknowledged but data will not be acknowledged.
STOP CONDITION
All communications are terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the NM24C32xxx to place the device in the standby power mode.
Write Cycle Timing
ACKNOWLEDGE
Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 4. The NM24C32xxx device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the NM24C32xxx will respond with an acknowledge after the receipt of each subsequent eight bit word. In the READ mode the NM24C32xxx slave will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode.
Device Operation
The NM24C32xxx supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving devices as the receiver. The device controlling the transfer is the master and the device that is controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the NM24C32xxx is considered a slave in all applications.
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH and reserved for indicating start and stop conditions. Refer to Figures 2 and 3.
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NM24C32 Rev. C.2
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NM24C32 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
Write Cycle Timing (Figure 1)
SCL
SDA
8th BIT WORD n
ACK tWR STOP CONDITION START CONDITION
DS500073-4
Data Validity (Figure 2)
SCL
DATA STABLE
DATA CHANGE
SDA
DS500073-5
Definition of Start and Stop (Figure 3)
SCL START BIT SDA STOP BIT
DS500073-6
Acknowledge Response from Receiver (Figure 4)
SCL FROM MASTER Data Output from Transmitter
1
8
9
Data Output from Receiver START Acknowledge
DS500073-7
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NM24C32 Rev. C.2
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NM24C32 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
DEVICE ADDRESSING
Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are those of the device type identifier. This is fixed as 1010 for all EEPROM devices. The next three bits identifies the device address. Address from 000 to 111 are acceptable thus allowing up to eight devices to be connected to the IIC bus. The last bit of the slave address defines whether a write or read condition is requested by the master. A "1" indicates that a READ operation is to be executed and a "0" initiates the WRITE mode. A simple review: After the NM24C32xxx recognizes the start condition, the devices interfaced to the IIC bus waits for a slave address to be transmitted over the SDA line. If the transitted slave address matches an address of one of the devices, the designated slave pulls the line LOW with an acknowledge. signal and awaits further transmissions.
transfer by generating a stop condition, at which time the NM24C32xxx begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress, the device's inputs are disabled and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
PAGE WRITE
The NM24C32xxx is capable of thirty-two byte page write operation. It is initiated in the same manner as the byte write operation; but instead of termination the write cycle after the first data word is transfered, the master can transmit up to thirty-one more words. After the receipt of each word, the device responds with an acknowledge. After the receipt of each word, the internal address counter increments to the next address and the next SDA data is accepted. If the master should transmit more than thirty-two words prior to generating the stop condition, the address counter will "roll over" and the previous written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence.
Write Operations
BYTE WRITE
For a WRITE operation, two additional address bytes, with 12 active bits, are required after the SLAVE acknowledge to address the full memory array. The first byte indicates the high-order byte of the word address. Only the four least signicant bits can be changed, the other bits are pre-assigned the value "0". Following the acknowledgement from the first word address, the next byte indicates the low-order byte of the word address. Upon receipt of the word address, the NM24C32xxx responds with another acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. The master then terminates the
Acknowledge Polling
Once the stop condition is isssued to indicate the end of the host's write operation, the NM24C32xxx initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the NM24C32xxx is still busy with the write operation, no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.
Byte Write (Figure 5)
S T Bus Activity: A Master R T SDA Line Bus Activity SLAVE ADDRESS WORD ADDRESS (1) WORD ADDRESS (0) DATA S T O P
1010 A C K
0000 A C K A C K A C K
DS500073-8
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NM24C32 Rev. C.2
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NM24C32 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
Write Protection
Programming of the upper half of memory will not take place if the WP pin is connected to VCC. The device will accept slave and word addresses; but if the memory accessed is write protected by the WP pin, the NM24C32xxx will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted.
transfer but does generate a stop condition, and therefore discontinues transmission. Refer to Figure 7 for the sequence of address, acknowledge and data transfer.
RANDOM READ
Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues a start condition, slave address and then the word address it is to read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to "1". This will be followed by an acknowledge from the NM24C32xxx and then by the eight bit word. The master will not acknowledge the transfer but does generate the stop condition, and therefore the NM24C32xxx discontinues transmission. Refer to Figure 8 for the address, acknowledge and data transfer sequence.
Low VCC Lockout
NM24C32xxx provides data security against inadvertent writes that could potentially happen during the time the device is being powered on, powered down and brown out conditions by monitoring the VCC voltage during a write cycle. Whenever a write cycle is started, the built-in circuitry starts to monitor the VCC level throughout the duration of the write command sequence until the master issues the required STOP condition to start the actual internal write operation. If the sensed VCC voltage is below 3.8V at any point during this monitoring period, the device prohibits the write operation and does not generate the ACK pulse. This low VCC lockout feature is only available for standard 5V device.
SEQUENTIAL READ
Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. The NM24C32xxx continues to output data for each acknowledge received. The read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. The data output is sequential, with the data from address n followed by the data n+1. The address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. After the entire memory has been read, the counter "rolls over" and the NM24C32xxx continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowledge and data transfer sequence.
Read Operation
Read operations are initiated in the same manner as write operations, with the exception that the R/W bit of the slave address is set to "1". There are three basic read operations: current address read, random read and sequential read.
CURRENT ADDRESS READ
Internally the NM24C32xxx contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n+1. Upon receipt of the slave address with R/W set to one, the NM24C32xxx issues an acknowledge and transmits the eight bit word. The master will not acknowledge acknowledge the
Page Write (Figure 6)
S T Bus Activity: A Master R T SDA Line Bus Activity SLAVE ADDRESS WORD ADDRESS (1) WORD ADDRESS (0) DATA n DATA n+31 S T O P
1010 A C K
0000 A C K A C K A C K
DS500073-9
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NM24C32 Rev. C.2
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NM24C32 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
Current Address Read (Figure 7)
S T A R T S T O P
SLAVE ADDRESS
1010 A C K
DATA
NO A C K
DS500073-10
Random Read (Figure 8)
S T A Bus Activity: R Master T SDA Line Bus Activity S T A R T S T O P
SLAVE ADDRESS
1010 A C K
WORD ADDRESS (1)
0000 A C K
WORD ADDRESS (0)
SLAVE ADDRESS
1010 10 A C K
DATA n
A C K
NO A C K
DS500073-11
Sequential Read (Figure 9)
S T Bus Activity: A Master R T SDA Line Bus Activity
A C K
SLAVE ADDRESS
DATA n
DATA n + 1
DATA n + x
S T O P
1010 A C K A C K A C K NO A C K
DS500073-12
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NM24C32 Rev. C.2
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NM24C32 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197 (4.800 - 5.004)
8765
0.228 - 0.244 (5.791 - 6.198)
1234
Lead #1 IDENT 0.150 - 0.157 (3.810 - 3.988) 8 Max, Typ. All leads 0.04 (0.102) All lead tips
0.010 - 0.020 x 45 (0.254 - 0.508)
0.053 - 0.069 (1.346 - 1.753)
0.004 - 0.010 (0.102 - 0.254) Seating Plane
0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads
0.016 - 0.050 (0.406 - 1.270) Typ. All Leads
0.014 (0.356) 0.050 (1.270) Typ 0.014 - 0.020 Typ. (0.356 - 0.508)
Molded Small Out-Line Package (M8) Order Number NM24C32xxxM8 or NM24C32xxxEM8 Package Number M08A
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NM24C32 Rev. C.2
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NM24C32 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) 0.092 DIA (2.337) Pin #1 IDENT Option 1 0.032 0.005 (0.813 0.127) RAD 0.250 - 0.005 (6.35 0.127) Pin #1 IDENT
8
7
8
+
7
6
5
1 1 2 3 4
0.039 (0.991) 0.130 0.005 (3.302 0.127) Option 2 0.145 - 0.200 (3.683 - 5.080) 0.040 Typ. (1.016)
0.280 MIN (7.112) 0.300 - 0.320 (7.62 - 8.128)
0.030 MAX (0.762) 20 1
95 5 0.009 - 0.015 (0.229 - 0.381) +0.040 0.325 -0.015 +1.016 8.255 -0.381 0.125 (3.175) DIA NOM
0.065 (1.651)
0.125 - 0.140 (3.175 - 3.556) 90 4 Typ 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) 0.060 (1.524) 0.020 (0.508) Min
0.045 0.015 (1.143 0.381) 0.050 (1.270)
Molded Dual-In-Line Package (N) Order Number NM24C32xxxN or NM24C32xxxEN Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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